In this paper, the design and the implementation of a pipelined hardware accelerator based on a fuzzy logic approach for an\nedge detection system are presented. The fuzzy system comprises a preprocessing stage, a fuzzifier with four fuzzy inputs, an\ninference system with seven rules, and a defuzzification stage delivering a single crisp output, which represents the intensity\nvalue of a pixel in the output image. The hardware accelerator consists of seven stages with one clock cycle latency per stage. The\ndefuzzification stage was implemented using three different defuzzification methods. These methods are the mean of maxima, the\nsmallest of maxima, and the largest of maxima.Thedefuzzification modules are interchangeable while the system runs using partial\nreconfiguration design methodology. System development was carried out usingVivadoHigh-Level Synthesis,VivadoDesign Suite,\nVivado Simulator, and a set ofXilinx 7000 FPGA devices.Depending upon the speed grade of the device that is employed, the system\ncan operate at a frequency range from 83MHz to 125MHz. Its peak performance is up to 58 high definition frames per second. A\ncomparison of this system�s performance and its software counterpart shows a significant speedup in the magnitude of hundred\nthousand times.
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